1. Field of the Invention
The present invention relates to a diode parallel-plate plasma CVD system forming a thin film constituting a semiconductor device and a method for producing the semiconductor device using the same.
2. Description of the Related Art
To form a thin film constituting a semiconductor device, a diode parallel-plate plasma CVD system has been used. The plasma CVD system of this type has such a construction wherein wafers are mounted with the surfaces thereof being downwardly directed for reducing particles (for example, as disclosed in Japanese Patent Laid-open No. sho 62-172732).
FIGS. 4a to 4c show a plasma CVD system of the conventional type having the above described structure: FIG. 4a is a side view; FIG. 4b is an enlarged view of the 4(b) portion shown in FIG. 4a; and FIG. 4c is a plan view of a wafer holder.
Referring to FIG. 4a, a reaction gas 8 is fed within a vacuum vessel 10 while an exhaust gas is discharged from gas exhaust ports 4, and thus the degree of vacuum in vessel 10 is kept at several Torr. In such a state, a low frequency power supply (50 KHz) applies a low frequency electric power across a diode parallel-plate type opposed electrodes composed of a wafer holder 2 serving as an upper electrode (ground electrode) and a lower electrode (power supply side electrode) 3, thus generating a plasma 9 therebetween to form a film on each of the wafers 1. In this case, a heater 12 supplies sufficiently stable heat to the back surface of the wafer 1. The heating plays an important role in forming a film having sufficient thickness and the preferable crystal structure on the front surface of the wafer 1.
However, the plasma CVD system mentioned above has a disadvantage in that sticking of the insulating film 11 on the peripheral portion of each wafer 1 often occurs, as shown in FIG. 4b, which makes the film formation slow and unstable. Namely, the insulating film 11, stuck on the peripheral portion of the wafer 1, insulates the wafer 1 from the wafer holder 2 serving as the upper electrode, thus potentially causing a defect in the film formation.
Taking this into consideration, see FIGS. 5a to 5e, which corresponds to the subject matter of Japanese Patent Laid-open hei 2-105527 and which proposes such a technique, i.e., covering the back surface of each wafer 1 mounted on a wafer holder 2 with a conductive material 16, and connecting the conductive material 16 to the wafer holder 2 (upper electrode) thereby securing the stability of the film formation. However, this technique has the following disadvantage. Since the wafer holder 2 serving as the upper electrode has a large area (e.g., a diameter of 700 mm), the use of a high frequency power supply (e.g. 13.56 MHz) allows the current to flow on the front surface of the electrode due to the skin effect or the like, thereby reducing the electric power contributing to film formation. Further, as shown, the electric power for generating plasma is spread across the whole area of the wafer holder 2, which causes the electric power to be dispersed thereby weakening the electric field distribution in the vicinity of each wafer (bringing about the tendency of reducing the plasma density in each wafer region). This lowers the generation amount of plasma in the vicinity of the wafer, which remarkably reduces the film formation rate. Therefore, in practical application, the diode parallel-plate plasma CVD system has used only a low frequency power of approximately 50 KHz.
However, the film formation using a low frequency power supply has the disadvantage of generating a compressive stress as an internal stress within the film, and of enlarging damage to an element due to ions, thereby deteriorating the reliability of the semiconductor device.